1. Field of the Invention
The present invention relates to integrated circuits (ICs), and in particular to a semiconductor structure with a through-silicon via (TSV).
2. Description of the Related Art
Through-silicon vias (TSVs) are often used in 3D integrated circuit devices and stacked integrated circuit dies for connecting dies. Integrated circuit (IC) dies are generally formed on semiconductor wafer substrates, such as silicon wafers, and the TSVs extend through the thickness of the wafer substrate extending from one side of the substrate to the other side, thereby connecting the integrated circuits on a die to the backside of the die.
Since the TSVs are metal vias extending through the thickness of the semiconductor substrate, the presence of the TSVs induce tensile stress in the surrounding semiconductor material. This requires that the TSVs to be kept at a distance apart from device circuits in the semiconductor wafer in order to avoid degrading the device circuits' performance. The necessity to keep the device circuits away from the TSVs defines a semiconductor region around a given TSV in which no device circuits are placed, and this region is referred to as a keep-out zone. The larger the keep-out Zone, the lower the area of the semiconductor wafer for forming the device circuits.
In order to maximize the area over the semiconductor substrate for forming the device circuits, it is desired that the design of the keep-out zone be compliant with the maximum area of the device circuits utilized.